1. Technical Field
The invention relates to methods of performing a photolithography process and methods of forming a semiconductor device using the same, and more particularly, to methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same.
2. Discussion of the Related Art
Recently, the semiconductor market has demanded development of a semiconductor device with a more competitive price as well as a high speed of data input/output and a high capacitance of information storage compared to existing semiconductor devices. In order to achieve these demands, semiconductor devices are presently being formed through reduction of the critical dimension (CD) of the design rule in order to form fine patterns of smaller size and spaces between patterns having a smaller width, while employing existing materials to maintain price competitiveness.
However, if the semiconductor device is formed with a design rule of smaller CD without further change of its structure under the condition as described above, the characteristics of the semiconductor device may deteriorate as a result. The deterioration of the characteristics of the semiconductor device may result through electrical or physical shorts between discrete elements due to the reduction of the design rule. Further, the short of the discrete elements deteriorates interconnection capability of the semiconductor device. This interferes with the fabrication of the semiconductor device while maintaining price competitiveness.
Technologies for solving the above-described problem are discussed in, for example, U.S. Pat. No. 6,329,306 (hereinafter, the '306 patent) to Shusi Nakao et al.
According to the '306 patent, the method includes forming first layers and second layers adjacent to the first layers, using two or more masks and photolithography processes twice. The first and second layers may be holes and lines respectively, or lines and holes respectively. The lines are formed to fill the holes and concurrently, to extend from the holes.
The fine patterning further includes performing etching processes corresponding to the photolithography process. However, the photolithography processes of the '306 patent have different photoresist layers with different (e.g., hole and line) patterns. For this reason, the fine patterning disclosed in the '306 patent necessarily may complicate the semiconductor formation process to form holes and lines. As such, this may lead to an increase in the production cost for the process.